21 September 2024 - 27 September 2024

Table of Contents

1. MIT OCW

1.1. 18.06sc (Linear Algebra)

1.1.1. Unit III: Exam 3

2. SJ grounds

2.1. Water leak

Mostly fixed. Need to stub out outside water galvanize pipe, which is unused and has it's own problems.

3. Lapuz Peking/Panerus

Laid out keys. Keys are to big for Burhan's "restaraunt" cases. Ray to think about the next steps.

4. Mill

4.1. Y axis servo and controller delivered to SCZ.

5. EDA workflow

5.1. FPGA programming

5.2. RV32I

Seeing if a very simple RV32I is possible at ~600 ice40 cells. Likely not possible with a barrel shifter unless a multiplier is used. Certainly won't be fast, if possible at all at this size. This comes out to 18 gates per bit, which seems to be a ridiculously low number. Need to refine counting methodology to count LUTs and flops separately. Maybe further refinements for post-placement utilization (for example, how many LUTs get combined with a flop vs. separate LUTs and flops).

5.2.1. 'almanor' RV32I

  1. Three port register file, simplify decoder (~1100 LUTs, 300 FFs, 4 BRAM)

    Not too happy with the result. Messier than expected.

  2. Refactoring

    Still trying to understand what's driving the gate count. need to do some scaling experiments (FF/LUT per bit for various constructs).

  3. Post-synthesis testbench

    Fragility much reduced after aggressive process splitting.

  4. Verilator testbench

    Started planning.

  5. CSR/Debug interfaces

    Seeing if it's worth it to implement minimal CSR and debug interfaces

  6. Picosoc analysis

    Understanding picosoc implementation as a reference

  7. Standard tests
    1. riscv-arch-test

      Ported and running. After changing verilog memory image generation to use objcopy, and correcting JALR masking, all RV32I tests pass.

    2. riscv-torture
      1. Used picorv32 patches to generate test cases.

        Tried generalizing the Scala code, but looks like it was going to require more changes than I was comfortable with making - particularly for the E reduced register profiles.

      2. Regex filter

        Wrote a regex based filter to change opcodes and various ranges for RV32I, RV32E and RV64E.

      3. Tests pass

        All torture tests pass.

  8. Compare with a pipelined implementation

    Still thinking about it.

  9. Debug and Interrupt architecture

    Working out what's needed.

5.3. RTX-2000

Pulled out the RTX-2000 manual. Going to be a slog if I do it.

5.4. Synthesizable sparc v8

5.4.1. Seeing what it takes to make 'bs' synthesizable.

No way. Need to start fresh.

5.4.2. make smaller than picorv32?

Want to see if I can get something substantially smaller than picorv32 - although I doubt it. Better to start with RV32I though.

5.4.3. Found a bug

in load base/offset register instructions.

5.4.4. Found maybe another bug

Not sure about condition codes on 'sub'. Difficulty porting to rv32 leads to questions.

5.4.5. Cleanups

Apparently never run though verilator. Cleaned up.

5.4.6. Need legion

Need to see if the UltraSparc 10 is still running for legion tests.

5.4.7. u10

  1. Serial port works so boot is trying to do something.
  2. Doesn't seem to respond to 'break'

    Enhanced 'sp' to send break command.

  3. NVRAM battery is dead. Not a FRU.

    Needs an invasive fix or part replacement. NVRAM held MAC address, so that would be unavailable so could explain not booting. DHCP database has programmed MAC for static IP assignment so that at least is recoverable.

  4. Video dongle.

    Dongle works with VGA monitor. Updating NVRAM parameters on console allows system to boot.

  5. Recovered legion

    Copied off legion simulator binaries.

6. Spark/QEMU

Tested QEMU sparc simulator running Solaris 5. Probably a reasonable alternative to using u10.

7. Cross compilers

7.1. Toolchain scripts running.

7.1.1. moxie-elf c, c++, and ada.

7.1.2. sparc-elf c, c++, and ada.

7.1.3. riscv-elf c, c++, and ada.

gdb riscv simulator seems to not handle logical right shifts correctly in 32 bit mode. Arithmetic right shift has specific checks for 32 bit mode, but logical right shift does not and is clearly right shifting a 64 bit value.

8. SCZ Front Step

8.1. Starting to fit.

Hanging up on something hidden.

8.2. Need to fix mistake under window.

Have a patch piece.

9. Spacewire-like PHY

Poking that this long-standing problem. Building infrastructure to test if it's possible to construct a PHY layer with acceptable BER to 50 MBit which should be sufficient for 32 16-bit channels at 48 KHz sample rate. Need to re-establish EDA workflow.

Not sure this is practical.

10. CA Root Key Generation

Nice to have an appliance that manages keys. Need to make this simple. Really don't have time for a science project. Too, bad, though. It kind of is a science project. Could just buy something from nitrokey https://www.nitrokey.com/ but I really don't want to spend money on it of I have hardware already. Looking at nitrokey in more detail, it doesn't seem to be any simpler than what I'm doing already.

10.1. First pass done

10.1.1. Based on https://pki-tutorial.readthedocs.io/en/latest/simple/

Interesting that the certs generated fail with openssl sserver testing because the cryptographic algorithms are too weak.

10.1.2. Work continues

  1. Have an outline with ECDSA/NIST-384
  2. Have consolidated configuration across CAs.
  3. Trying to decide if/how to deal with revocation. What a PITA.

10.2. Need to be clear on security properties.

Definitely protect against remote access to private keys. How strong does the protection against local access need to be?

10.3. Simple hardware.

10.3.1. Use beagleboard with local interface

10.3.2. Use some modern device TPM

Need to export data for backup.

10.3.3. Or something that uses PKCS11 interface

10.4. USB Serial interface only but no credentials across USB I/F.

But this potentially exposes the hardware to remote access via the USB I/F when connected.

10.5. Use Sneakernet

Doesn't scale. Should use something so cert updates are automatable. But that's a science project it seems.

11. Compilers

11.1. Compiled Wikipedia PL/0 example

11.2. Work out overall plan.

Lots of moving pieces.

11.3. Looking into LLVM MLIR.

Will not use immediately, but perhaps trend in that direction.

11.4. ASDL

11.4.1. current smlnj C++ implementation incomplete

11.4.2. old versions asdl source fail to build with new versions of smlnj

11.4.3. old versions of smlnj not easily buildable on x8664

11.4.4. ancient binary of asdl 1.2 compiler seems to work

but associated libraries are to old to link because of missing ctype symbol

11.4.5. analyzing asdl 1.2 generated code

Most of the code is for serialization, which is going to be replaced anyway, so can be removed by hand.

11.4.6. run in vm?

Analysis of binaries shows that it was built on some redhat os using gcc 2.8.1. Redhat-6.2? No. Tried various ancient Redhat OSs.

12. Piper dovecot

12.1. Update broke dovecot auth.

Looks PAM related, but PAM update failed to fix.

12.2. Set tuffy up as a staging server

So I don't debug on 'production'.

12.3. piper dovecot SSL certificate NOT broken

At least not obviously broken (yet). Further investigation needed.

13. Various i686

13.0.1. netbsd

was installed. But needed the box for something else.

13.0.2. buildroot

builds complete.

14. piper

14.1. dovecot

14.1.1. Raising apparmor error.

Not sure how to resolve.

14.2. pidgeonhole

14.2.1. procmail replacement.

14.2.2. Considering integration.

14.3. httpd

14.3.1. Still stable.

But seems to occassionally mis-serve files.

14.4. SSL cert

Trying letsencrypt with certbot. http problem above may be interfering.

14.5. redmine

Still not sure I want to go down this rabbit hole.

14.6. openvpn

Need to consider cert construction.

15. Buffalo WZR-HP-G300NH

15.1. Update

Sometime next year.

16. SJC weather station

16.1. Proper enclosure mostly constructed

16.1.1. Needs a redo on bottom plate

16.1.2. Seems to have improved wireless connectivity somewhat

17. opencl

17.1. Studying. Have some examples working.

17.2. Need to look at arrayfire as an alternative.

17.3. This is a bit of a hammer looking for a nail.

18. EPLDH

18.1. MPFI interval arithmetic better alternative

19. wktpqb

19.1. needs a new approach

19.2. Verifying edge construction (con't.)

19.3. 'gcd' algorithm doesn't work

20. Mill Controller #2

20.1. Mounted on mill - ready or testing

20.2. Need to investigate new HW/SW for eventual replacements

20.2.1. Old crap ain't gonna last forever

20.2.2. Buildroot/Linux 5.15 PREEMPT + latency tools

First pass done - boots on real hardware

20.3. Alternative architecture

20.3.1. Split off stepper motor controller to separate board

Increase latency tolerance on controller

20.3.2. Use emc2 MODBUS/TCP protocol for stepper and other IO

21. Alum Rock Data Center

21.1. May have problem with network power module.

It's only 30 years old or something like that.

21.2. Added Ethernet card to tuffy

Preparing as backup/staging server.

21.3. Need a VPS with static IP

Just use dynamic interface to bind.

22. Virtual Orchestra

22.1. sfz file tests

22.1.1. need tooling to edit sample files

22.2. increasingly skeptical whether quality results are possible

22.3. maybe should treat as platform for concatinative synthesis

22.4. maybe should just accept the limitations and work with it

One should not be disappointed that a guitar can't sound like a flute.

23. gat

23.1. spectrogram done - matches 'octave' output

24. RIOT drivers

Implemented - needs testing.

24.1. WS2801

24.2. Velleman KA03

24.3. Velleman KA05

25. mcd05 32 button/led box

25.1. Recovered schematics.

25.2. Planning software.

25.3. Received STM32F767 Nucleo144 with Ethernet.

25.3.1. Test program running.

25.3.2. Need to consider CoAP multicast discovery.

25.3.3. Consider simpler architecture with STM32F767 as a 'hub'.

25.3.4. Consider CAN interface to hub.

26. AMD 2900 bitslice computing

26.1. Probably my oldest uncompleted project

26.2. Exploring possibilities for something constructive

Create verilog models for 2903/2910 and verify against hardware?

27. Hitachi HD68B09E CPU

27.1. RAM/UART/IO

27.2. Started schematic

27.2.1. Standard peripheral set for 8 bit CPU bringups

Board schematic planned - need Kicad symbols

27.3. Arduino Mega 2560 DMA loader

…Along with standard 8 bit loader

27.4. Generate quadrature clock directly

27.5. Full Bus SW Emulation infeasible

6809 1000ns maximum cycle time too short

28. Rockwell R65F11

28.1. Still evaluating.

28.2. Dev board

Reverse engineered some of a mostly fully built development board with one part missing. As near as I can tell, that one part is some sort of programmable address decoder with a pinout that does not correspond to any part I can find. Kind of like a GAL but with inputs on top and outputs on bottom (as opposed to left and right in a standard GAL). I have no idea what the provenance of this board is and if it ever worked.

29. PLD programming

Looks like Atmel 16V8 is the last 5V PLD part left standing. Maybe not surprising that there still doesn't appear to be a fully open source tool chain for programming. How hard could it be? (!) Could next-pnr generic help? Might be easier to use espresso for logic array and program output logic bits directly for simple stuff.

30. EPROM Programming

Found some software for Needham programmer. Need to check electrolytic caps on ISA board.

31. POSIT

31.1. Use POSITs for YRX?

No. Existing library is fine.

32. MAME

32.1. Subset builds in debug mode

Full debug fails - not enough disk or memory.

32.2. gs6809 serial IO doesn't work right with PTY and other streams

32.3. ampro (Z80/Z80SIO) does work with PTY

32.4. Evaluating what is needed for other emulators.

33. More project ideas

33.1. Zuse Z3 simulation in Verilog

Good excuse for floating point ALU design. Try posit format?

33.2. GMPForth ports to simulators

33.2.1. SIMH for some targets (vax)

33.2.2. MAME looks interesting for microprocessor system emulations

How to support ersatz systems?

33.2.3. Ports to classic figFORTH targets

33.3. GMPASM assembler

May be useful for handbuilt and rare systems (DMX1000?).

33.4. Extracting ISO Superboard Forth ROMS for MAME emulation

33.5. 'bwocl' OpenCL tooling

33.5.1. Offline compilation

33.5.2. Standard Kernel Running

33.6. hardware support for classic 5V CPUs

33.6.1. RTX2000, CDP1802 still available!

33.6.2. 6502, 68000, 320C30, others on hand

33.6.3. CPUs with totally async bus may be supportable without RAM

33.6.4. Could use small footprint monitor in asm (gmpmon?)

33.7. Existing 'retro' hardware still working?

33.7.1. OSI Superboard

Unknown. Composite to VGA adapter didn't seem to work. Needs analysis. Found OSI model 610 board underneath!

33.7.2. Super Jolt

No output. Needs analysis.

33.7.3. Ampro Little Board

Not booting. Needs analysis.

33.7.4. Rockwell R65F11 Demo board

UART sending "NO ROM" at 2400 7N1 as expected with 2MHz xtal. MAME emulator possibilities?

33.7.5. NMIX-0016

Works. Found original prom in a parts stash(!).

34. David Davies

34.1. Broadcom (BCG?) Employee indicted for running a brothel.

34.2. New case C1923172, consolidated with 15 Parties.

34.3. Court website no longer allows seaching (grrr!)

Author: Daniel Kelley

Created: 2024-10-05 Sat 08:02

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