Simple Synchronous FIFO

Daniel Kelley

20 August 2020

0.1 Introduction

The Simple Synchronous FIFO is a First In First Out (FIFO) memory with a common clock and a synchronous reset. The data width and memory depth is parameterizable.

(image)

Signal	Direction	Description
dout	Output	Read Data
full	Output	Write full
empty	Output	Read empty
din	Input	Data in
w_en	Input	Write Enable
r_en	Input	Read Enable
clk	Input	Clock
rst	Input	Reset

0.2 Verilog

  module sfifo
 #(parameter DW = 8,
      parameter AW = 4)
  (output [DW-1:0] dout,
      output      full,
      output      empty,
      input [DW-1:0] din,
      input       w_en,
      input       r_en,
      input       clk,
      input       rst);